Silicon technology is limited for power transistor applications, and is being replaced by SiC and GaN technologies. However, SiC behaves differently than Si during device fabrication. Also, Si power transistors often include a separate p-n junction integrated with the transistor device. The integrated p-n junction is formed by dopant implantation and annealing, and serves as a freewheeling diode during operation. For example, buried p-type regions for an n-channel power transistor function as compensation regions which shape the electric field when the device is blocking.
Unlike Si technology, annealing in SiC activates dopant elements but does not cause meaningful diffusion deeper into the crystal structure. To create a buried dopant profile such as for an integrated p-n junction, implantation typically must be performed multiple times and with relatively high energy. Implant energies in the MeV range are needed to yield an acceptable dopant profile. For such high energies, a very thick oxide mask is usually required which further increases process cost. Also, often it is not possible to implant the required dose at the required position or depth due to geometrical or process constraints, adding to the process costs while also increasing the risk of creating a large amount of crystal defects in the SiC substrate. In addition, the annealing temperature for dopant activation is very high and seldom heals crystal defects generated during implantation. These defects remain in the device, and may cause hazardous effects such as bipolar degradation during device operation. Moreover, implantation may result in a tail which causes variation/mismatch between adjacent buried doped regions. The variation/mismatch may affect the gate oxide shielding ability of the buried doped regions since the distance between adjacent doped buried regions determines shielding effectiveness.
Thus, there is a need for an improved technique for forming a buried doped region of a SiC device.